Hardware Deep Dive: Siemens and NVIDIA Push Agentic EDA Into 3D IC Electrothermal Signoff

Every accelerator generation tightens the same three constraints: power delivery, memory bandwidth and heat removal inside a package that has stopped growing. For teams evaluating stacked silicon, the schedule risk usually sits in reconciling electrical, power and thermal data rather than in the compute die itself. The refreshed agentic EDA portfolio from Siemens and NVIDIA targets that reconciliation step: it couples the agentic AI capabilities introduced at DAC 2026 with NVIDIA accelerated computing, drives a single workflow across seven EDA tools, and evaluates hundreds of design points per cycle.

Benchmark numbers at a glance

Before the architecture details, isolate the quantitative claims, because they are the only measurable figures attached to the update. Siemens published the following from benchmark studies comparing the agent-orchestrated flow against manual workflows:

• Engineering effort: up to a 95% reduction in engineering effort
• Flow bring-up: up to a 99% reduction in workflow setup time
• Exploration breadth: up to 50 times greater design exploration coverage

Each value is a ceiling, not a floor, and the baseline is hand-driven coordination rather than a partially automated in-house flow. Teams that already script their own tool bridges should expect a smaller delta than the headline numbers imply.

Why the package is the trigger

AI systems require larger compute capacity, greater memory bandwidth and more thermal management inside compact packages. The Rubin GPU is the concrete reference point here: up to 50 petaflops of NVFP4 inference and up to 288 GB of HBM4 per GPU. Those GPUs combine into systems such as NVIDIA Vera Rubin NVL72. When compute and memory integrate more closely, power density and heat concentration rise with them, which is the argument for treating electrothermal co-design as a design-phase activity instead of a final-verification chore.

The coordination tax being removed

Conventional 3D IC work spreads across specialists. Electrical, power, thermal and extraction owners each run separate tools, transfer data between domains, and repeat evaluations at every iteration. As complexity increases, time and compute constraints push teams to shrink the number of scenarios evaluated, so power or thermal defects surface late. The new coordination layer aligns Siemens electrothermal analysis tools through one workflow, while the Siemens Design Space Exploration and Optimization (DSE/DSO) technology lets engineers test and validate alternatives against physics-based signoff solvers.

Inside the agent loop

An engineer defines the design objectives. The Fuse EDA AI Agent, integrated with Intelligence Center X, then orchestrates the Siemens tool chain: it runs coupled electrothermal analyses, identifies unmet targets and evaluates whether the cause lies in power delivery, placement, materials or a combination of factors. Analysis results steer design-space exploration and trade-off assessment, after which selected configurations are rerun against the original objectives. The net effect for hardware programs is earlier visibility of power and thermal issues.

Taken as one execution, the workflow coordinates nine steps across seven Siemens EDA tools, performs 50 to 100 reasoning steps during an eight- to 10-hour runtime, and sweeps heat transfer coefficient (HTC) boundaries, power budgets and material stack-ups over 200 to more than 500 design points per cycle. The table maps each reported parameter to its operational meaning.

Reported parameter	Value	Operational read-out
Orchestration span	nine steps across seven Siemens EDA tools	Most cross-domain hand-offs collapse into a single run
Reasoning depth	50 to 100 reasoning steps	Root-cause triage happens inside the loop, not after it
Cycle time	eight- to 10-hour runtime	One exploration cycle fits an overnight batch window
Design-point throughput	200 to more than 500 design points per cycle	Scenario lists stop being trimmed purely for wall-clock reasons
Inputs swept	HTC boundaries, power budgets, material stack-ups	Cooling and packaging assumptions become testable variables
Effort delta vs manual	up to a 95% reduction in engineering effort	Specialist hours shift from data transfer to judgement
Setup delta vs manual	up to a 99% reduction in workflow setup time	New corners of a program gain analysis coverage faster
Coverage delta vs manual	up to 50 times greater design exploration coverage	Trade-off curves replace single-point guesses

Tool chain: which engine does which job

The workflow is only as credible as the solvers it drives. All seven are signoff-grade Siemens products, and each owns a distinct slice of the electrothermal problem:

• Innovator3D IC Integrator software — floor planning, 3D IC assembly and package design.
• Solido Characterizer software — library characterization to generate Liberty files.
• mPower Digital software — power analysis, including temperature-dependent instance power.
• Calibre 3DThermal software — 3D IC thermal signoff and power mapping.
• Simcenter Flotherm software — system-level thermal simulation and visualization.
• Calibre xACT software — temperature-dependent parasitic extraction.
• Solido SPICE software — power- and temperature-aware electrical SPICE simulation.

The pairing that matters most for 3D IC hardware decisions is the closed loop between mPower Digital software (temperature-dependent power), Calibre xACT software (temperature-dependent parasitics), Calibre 3DThermal software (thermal signoff and power mapping) and Simcenter Flotherm software (system-level heat removal). That loop is what allows a thermal boundary condition and a power budget to be varied against each other instead of being frozen by four separate teams.

The compute and agent layer underneath

Siemens combines the NVIDIA Agent Toolkit with NVIDIA accelerated computing and CUDA-X libraries so that accelerated simulation tools feed analysis results into the agents during design exploration. On the NVIDIA side, the stack breaks down as follows:

• Nemotron open models — orchestration and execution of agentic EDA subflows.
• NeMo Gym — tracks agent trajectories and pinpoints where agent skills and Model Context Protocol (MCP) tool descriptions need refinement.
• NeMo RL — post-training fine-tuning of language models with EDA knowledge and tool-calling capability.
• NeMo Relay — observability and audit records across agent harnesses.
• NeMo Switchyard — routes tasks according to compute requirements, accuracy and token costs.
• NVIDIA OpenShell — sandboxes agent execution to help protect intellectual property and foundry process design kits (PDKs).
• NVIDIA CUDA-X libraries — accelerate the supported engineering solvers used in the workflow to cut simulation time across iterations.

Four readings to avoid

• Thermal analysis belongs only at signoff. The premise of the update is that electrothermal co-design moves into the design phase, precisely because power density and heat concentration rise as compute and memory tighten.
• Agents replace signoff solvers. They do not. Alternatives are still validated against physics-based signoff solvers; what changes is who sequences the tools.
• Accelerated compute alone delivers the numbers. The reported effort and setup reductions are attributed to the coordination layer plus DSE/DSO exploration, with NVIDIA accelerated computing as the execution substrate.
• 95 percent and 99 percent are contractual expectations. They are benchmark-reported ceilings measured against manual workflows, and heterogeneous legacy flows rarely match that baseline.

Action guidance for hardware and procurement teams

1. Inventory the hand-offs first. Count how many steps your current 3D IC program needs in order to move data between electrical, power, thermal and extraction domains; that count is your comparison point against nine steps across seven Siemens EDA tools.
2. Convert cooling assumptions into variables. If your team fixes HTC boundaries early, test whether varying them across 200 to more than 500 design points per cycle changes the package choice.
3. Schedule around the batch. Treat an eight- to 10-hour runtime as an overnight cycle and align review gates to the completed run rather than to intermediate tool output.
4. Audit the agent path. For programs under foundry PDK restrictions, confirm how NVIDIA OpenShell sandboxing and the NeMo Relay audit record cover delegated subflows before you hand work to an agent.
5. Re-baseline capacity planning. When a single cycle evaluates hundreds of design points per cycle, compute-hour forecasts scale with exploration breadth rather than with the number of manual runs.

The hardware takeaway from the DAC 2026 cycle is not that another agent demo shipped, but that the metrics shifted from accuracy claims to throughput claims: reasoning steps per run, hours per cycle, design points per cycle. For accelerator and stacked-memory programs, that reframes EDA tooling as a compute-capacity decision sitting in the same conversation as Rubin GPU selection and NVIDIA Vera Rubin NVL72 system planning — and it makes the cost of evaluating a few hundred extra alternatives look very different from the cost of the manual loop it replaces.