MyTechDailyNews Hardware: Inside Macronix's 2026 Memory Tier Map — Specs, Pricing and Buying Signals for NOR, SLC NAND and eMMC
By Sarah Chen · MyTechDailyNews Hardware desk · Tech Daily
Nobody in a board review argues about boot flash until a purchase order comes back nine months out. That is exactly what has changed in nonvolatile memory: the small, unglamorous parts holding firmware next to every controller now behave like strategic components. Macronix, a lead supplier of NOR flash, SLC NAND and eMMC, frames the shift as structural rather than a normal inventory swing — AI capacity demand is re-pricing and re-architecting the memory stack from the accelerator down to the socket. This Hardware desk briefing reads that argument the way a designer or a purchaser has to: measured figures, roadmap nodes, interface voltages and the ordering decisions that follow.
Five numbers that set the tone
- NT$37.8 billion — Macronix's raised capital expenditure budget for 2026, pointed at 12-inch wafer capacity for 3D NOR, NAND, eMMC and adjacent products.
- $20 billion to $70 billion — the memory market passed $20 billion in 2025 and may approach $70 billion in 2026, with growth carried by price rather than bits shipped.
- around $24 billion — the company's 2026 estimate for the combined NOR flash, SLC NAND and low-capacity eMMC (≤32GB) cluster.
- sixfold — the approximate price climb over the past year, traced to supply and manufacturing structure rather than end-device demand alone.
- two to three years — the realistic lag between booking new capacity and shipping yield-correct parts.
What Macronix International told EE Times Taiwan, translated into design consequences
Martin Lin, director of marketing at Macronix International, put it bluntly in an interview with EE Times Taiwan: the AI effect is not simply “more memory required”, it is that “the entire memory architecture is changing.” NOR flash is turning up in more AI servers, engineers are hunting a tier that delivers more capacity per dollar than HBM, and key value (KV) cache has become a first-order input to inference throughput.
Read as a hardware story, that single sentence relocates memory from a line item to a co-design constraint. Boot density, interface width, latency budget and standby current now share the same spreadsheet as accelerator choice. Macronix's own answer is a push toward denser, lower-power and more reliable designs across NOR, NAND and eMMC, funded by the lifted 2026 capex of NT$37.8 billion for 12-inch expansion.
MemFlation: pricing arrived before volume
Memory prices are still climbing. Structural changes in supply and manufacturing have pushed them up sixfold over the past year, and Macronix has a label for the mechanism: “memory inflation,” or “MemFlation.” The company's framing is that this is no inventory-cycle recovery. Samsung, SK Hynix and Micron have redirected capacity and capital spending toward high-bandwidth memory (HBM) and advanced server memory, mature-process capacity has been squeezed, and supply flexibility for NOR flash, SLC NAND and eMMC narrowed with it. NAND repriced separately as AI data centers and enterprise solid-state drives (SSDs) absorbed supply.
For buyers, the calendar matters more than the headline. NOR flash, SLC NAND and eMMC prices are expected to move higher in the third and fourth quarters of 2026 and then hold at elevated levels. Fresh capacity does not fix that quickly: equipment installation, process qualification and yield ramp-up can take two to three years, if not longer, so the supply gap cannot be closed on a schedule anyone can sign. As AI demand keeps crowding out mature-process capacity, automotive-market supply constraints and pricing pressure should become more visible starting in 2027.
Price behaviour also differs by product, which changes which line item you defend first.
| Product | Supply/pricing read for 2026–2027 | Design and procurement lever |
|---|---|---|
| NOR flash | Relatively moderate price increases, cushioned by earlier capacity investments | Consolidate firmware images onto higher-density Octal/xSPI devices; free board slots |
| SLC NAND | Heavier supply pressure; distributor commentary in 2026 puts second-half contract gains in the triple digits versus the first half | Sign long-term agreements early and qualify a second source before layout freeze |
| Low-capacity eMMC (≤32GB) | Automotive and industrial embedded builds flagged as the tightest allocation categories by market trackers | Build 40–64GB drop-in headroom into the next board revision |
Macronix expects the combined market for NOR flash, SLC NAND and low-capacity eMMC (≤32GB) to expand significantly, reaching around $24 billion in 2026, driven by higher shipments plus price increases caused by constrained supply.
Rack-level device counts: the “quantity” symptom
These flash devices mainly serve boot-up, firmware, system control and security functions. Lin notes that conventional servers typically required only about three to five flash devices, while AI servers use many more as baseboard management controllers (BMCs), network switches, retimers and other control components increase. Third-party trackers describe the same mechanism from the demand side: NOR content per AI server runs several times that of a conventional machine, partly because each management or retimer chip expects its own firmware device. Flash consumption per rack has therefore risen rapidly. Lin said, “The previous-generation rack had around 600 to 800 devices. The latest generation now has more than 1,000”.
The tier the industry is looking for under HBM
If rack device counts are a quantity problem, the search for new memory tiers beyond HBM is the deeper architecture change. AI training and inference lean heavily on HBM for the bandwidth GPUs need, but as models grow, HBM capacity and cost become limiting. Lin said that “only HBM is fast enough” today, while adding capacity and stacking more HBM layers also raises costs, so designers want tiers offering greater capacity and better cost efficiency.
High-bandwidth flash (HBF) is one emerging answer. Built on 3D NAND and paired with high-speed interfaces and high-density packaging, HBF tries to balance bandwidth, capacity and cost, moving data that does not need to stay in HBM into higher-capacity, relatively lower-cost NAND flash. The industry is also exploring AI server architectures that use SSDs with a high level of input/output per second (IOPS), where low-latency SLC NAND handles the large volumes of random data accesses required by GPUs and improves GPU utilization.
| Tier | Physical basis | Strength | Current limitation | Typical home in an AI box |
|---|---|---|---|---|
| HBM | Stacked DRAM | Highest bandwidth | Capacity ceiling, cost per GB | Latency-sensitive, hottest working data |
| HBF | 3D NAND + high-speed interface, dense packaging | Capacity per dollar with HBM-class bandwidth targets | Still pre-volume; industry reporting has samples in the second half of 2026 and first inference hardware in early 2027 | Warm model weights, long-context data |
| High-IOPS SSD | Enterprise NVMe | Bulk capacity, tier-friendly | Higher access latency | KV cache offload, historical context |
| Low-latency SLC NAND | Single-bit-per-cell NAND | Predictable random reads | Cost per bit, shrinking supplier base | GPU burst traffic, embedded logging |
| NOR flash | 55nm moving to 42nm, 3D NOR in development | Instant-on boot, firmware integrity, security | Small per-device capacity | BMC, switch and retimer control |
KV cache turns memory policy into a design decision
Tiered architectures matter most in AI inference. Large language models (LLMs) and agentic AI workloads must continuously retain conversation, task and historical information, so KV cache grows without a natural ceiling. Citing continuous AI conversations, Lin said that if memory capacity is insufficient, “you have to discard the earlier information.” Open-source serving stacks already behave as if that warning is live: they push KV blocks down to CPU DRAM and local NVMe so long sessions keep prefix hits instead of recomputing attention from scratch.
Future AI systems can organize data into different tiers according to data age, access frequency and latency requirements. The most frequently accessed and latency-sensitive data can remain in HBM, while larger volumes of data that do not require consistently high-speed access can move to flash, SSDs and other tiers. At the recent Future Memory and Storage conference (FMS 2026) in the United States, Macronix presented its dual-tier SSD architecture as a solution for KV cache offloading, exploring how different memory and storage tiers distribute AI workloads.
Data movement, not FLOPs, is the new bottleneck
As AI accelerators keep gaining compute capability, system bottlenecks are shifting from raw compute speed to whether data arrives in time. Lin said, “The GPU is already fast enough, but now , memory is actually too slow”.
Repeatedly moving data among the CPU, GPU, HBM, DRAM and storage devices consumes bandwidth and adds latency and power consumption, so simply raising processor speed may not improve overall system performance effectively. To cut that transfer tax, the industry is revisiting memory-centric AI and processing-in-memory (PIM) architectures, bringing computation closer to memory and, in some cases, letting memory perform simple operations before outputting results. Published PIM work — SRAM-attached arrays, DRAM-side logic and LPDDR-PIM variants — reports the main saving in energy per byte moved rather than peak throughput, which matters most for edge boxes on a fixed power envelope.
“Memory-centric AI” is not new: Macronix Chairman and CEO Miin Wu proposed it as early as 2019. As models, datasets and inference workloads grow, the idea is drawing attention from industry and academia again. Lin believes the next stage of AI performance gains will depend not only on faster GPUs but on more efficient memory architectures — where the data is, how it is moved and when it is processed.
Portfolio roadmap: density, voltage and layer count
Macronix's three major flash product lines continue to evolve toward higher density and greater capacity. Beyond raising supply of high-density NOR flash already used in AI servers, the company is expanding NAND and eMMC portfolios and advancing 3D NAND to cover more capacities and applications, currently with 48-layer and 96-layer products in mass production and higher-layer-count technologies in development. Automotive, communications, medical and aerospace are the reliability targets. For AI, industrial and embedded power budgets, low-voltage flash is progressing from 3V and 1.8V toward 1.2V.
| Product line | Roadmap direction | Key nodes |
|---|---|---|
| NOR flash | Higher density, lower power, greater reliability | 55nm to 42nm; 42nm in 2027; 3D-32-layer in 2028 |
| SLC NAND | Long-term supply support | Low-latency role in AI random access |
| eMMC | Higher capacity and density | 3D-48 and 96 layers to 192 layers |
Four misconceptions this cycle keeps generating
- “Cheap boot flash means the BOM is safe.” NOR, SLC NAND and eMMC were commodity items only while mature capacity was abundant; prices have moved sixfold and lead times follow price.
- “HBM solves memory for inference.” Bandwidth without capacity is a cost problem, which is why tiers under HBM are being standardized.
- “New fabs will relieve 2027.” Equipment installation, process qualification and yield ramp mean two to three years, so automotive and industrial allocation tightens before it eases.
- “More compute always fixes throughput.” Once data movement dominates, extra accelerator speed converts into idle time and watts.
Action list for the next 12 months
- Re-quote now, not at layout freeze. Treat NOR, SLC NAND and eMMC as long-lead parts through the third and fourth quarters of 2026, and price locks accordingly.
- Dual-source before silicon. Qualify at least two suppliers at the design stage; second-sourcing after a shortage is measured in quarters of revalidation.
- Design for density headroom. Move to higher-capacity NOR and 40–64GB eMMC footprints so a single firmware expansion does not force a board re-spin.
- Check supply voltage compatibility. Verify your controller rails before specifying parts still at 3V or 1.8V, since the migration path runs toward 1.2V.
- Pilot new tiers, do not default to them. HBF and dual-tier SSD offloading look credible on paper, but volume evidence lands in 2027 at the earliest.
- Book automotive-grade parts early. Constraints and pricing pressure are expected to show from 2027, and automotive qualification is the slowest to re-source.
Where to see the silicon
Macronix will showcase its latest nonvolatile memory technologies and application solutions — including automotive electronics and edge AI — at electronica 2026, held November 10–13 in Munich, Germany. Look for the vendor in Hall C5, Stand 279. For anyone whose roadmap depends on flash rather than HBM, that booth is worth the trip: the tier map being drawn this year decides what a platform costs and ships like two generations from now.
