MyTechDailyNews: Hard-to-Find NOR Flash Is Giving MRAM a Shot at AI Servers, Data Centers and Satellites

Buying a small memory chip used to be the most boring part of building a device. Lately, buyers say it can decide whether a project ships on schedule. That change in the supply picture is why Everspin Technologies is suddenly getting attention well beyond its industrial customer base: the maker of magnetoresistive random-access memory (MRAM) wants its parts designed into AI servers, data centers and satellites, on the argument that AI workloads need non-volatile memory that behaves more like working memory than like storage.

Below is the general-reader version of that story: what shifted, why a shortage is an opening, which numbers are public record, and what to watch next.

Five Things to Know Up Front

1. The trigger is availability as much as speed. A TrendForce report estimated NOR flash contract prices rose by a cumulative 100% to 120% in the first half of 2026, with AI-related demand absorbing much of the limited supply.
2. The pitch is substitution. “Now people cannot buy NOR flash,” said president and CEO Sanjeev Aggarwal, who frames MRAM as the only stand-in for standalone or discrete products.
3. The prize being claimed is large. Aggarwal puts the gap left by NOR flash at an opportunity worth $3 billion in 2028 or 2029, with a product under development on TSMC's manufacturing process.
4. AI is the lab, orbit is the proof so far. A Compute Express Link (CXL) demo explores MRAM as a memory tier, while a satellite bus has already flown an Everspin part.
5. None of this is finished-goods news yet. The company's AI-server work with MaxLinear is a memorandum of understanding, an evaluation framework rather than a shipping product.

Why a Memory Alternative Suddenly Sounds Reasonable

In an exclusive interview with EE Times, Aggarwal treated the technology as a way to route around the limits of current memory. “If you care for performance, I think that MRAM is the only solution we have,” he told EE Times.

Customers, he said, are evaluating MRAM for two separate reasons at once: performance and reliability on one side, and the simple difficulty of obtaining certain NOR flash products on the other. The TrendForce report placed NOR flash among the first memory categories to run into longer lead times and allocation, and noted that suppliers had not announced major capacity expansion.

“Most of the fabs in Asia have converted from NOR flash to DRAM. Much better profit margins. Then what is the alternative? MRAM is the only alternative for standalone or discrete products. And that is where they approach us.”

The pricing story is where a general audience should pay attention, because it changes the buying decision rather than the physics. Aggarwal said MRAM previously cost about three times as much as NOR flash, and that the distance narrowed to about 1.5 times once NOR flash prices climbed under supply constraints. “If you are going to use two NOR flash chips, you might as well just use one MRAM and be more cost-effective,” he said.

A TrendForce chart dated June 2026 covers supply-demand conditions and pricing outlook for SLC NAND and NOR Flash in the second half of 2026.

The arithmetic still depends on the application: how many chips a design needs, and which performance and reliability specifications it must satisfy. Aggarwal said Everspin's distributors had begun requesting cross-reference information so customers could locate MRAM alternatives when particular NOR flash components went unavailable.

How MRAM Compares With the Other Options on the BOM

Memory type	Job it usually does	What the record in this story says
NOR flash	Standalone / discrete code storage	Cumulative price rise of 100% to 120% in the first half of 2026; longer lead times and allocation
MRAM (Everspin)	Persistent memory between working memory and storage	20 to 30 nanoseconds; specified range of minus 40°C to 125°C; densities from 128 kilobits to 1 Gb
DRAM	Working memory	Operates on a nanosecond timescale
NAND flash	Storage	Access can take hundreds of microseconds
FRAM	Low-power non-volatile niche	Lower available densities
NVSRAM	Non-volatile SRAM role	Can present tradeoffs in reliability and operating conditions

Reasons customers pick MRAM, in Aggarwal's account, are reliability, SRAM- and DRAM-like performance, and read-write endurance.

The company's own finances set the bar for how much this pivot has to deliver. According to its annual report filed with the U.S. Securities and Exchange Commission (SEC), Everspin reported revenue of $55.2 million for 2025, up 9.5% from $50.4 million in 2024. Aggarwal said he expects the company to double revenue over three to four years, with the NOR flash opportunity plus demand from data centers, aerospace and defense, low-Earth-orbit (LEO) satellites, and industrial automation feeding that ambition.

The CXL Demo: Filling the Pause Between Memory and Storage

At the Storage Networking Industry Association (SNIA) Developer Conference in Santa Clara, California, Everspin showed MRAM modules paired with a Compute Express Link (CXL) controller. The setup produced a pool of persistent memory reachable through CXL.mem, the protocol that lets a system address memory across a CXL connection.

The intent, as Aggarwal described it, is to position MRAM as an extra layer sitting between DRAM, which acts as working memory, and NAND flash, which provides storage. Data that has to travel from processing down to slower storage can stall a workload. “Our memory is 20 to 30 nanoseconds,” he said. “You can use it for storage as well as compute, reducing the gap between NAND storage and DRAM working memory.”

Proposed duty: hold data produced during AI processing before it moves to longer-term storage. That could mean key-value (KV) caches, checkpoints, and information waiting on a write. A KV cache keeps data an AI model reuses while generating a response; checkpoints let a job resume after a failure.

Density is the honest constraint. Everspin's densities currently reach one gigabit, though Aggarwal said devices could potentially be stacked to deliver 8 Gb or 16 Gb. His counter is that a tier holding intermediate data only temporarily would not have to match NAND flash capacity.

Elsewhere on the roadmap sit higher-density parts and newer interfaces. Everspin has supplied IBM's FlashCore Modules and wants to grow its data center business past its existing DDR4 interface. “Our demonstration of the CXL protocol with our existing DDR4 chip will start getting us some entry into the data center market,” he said. “And by the time we have a good foothold, we will have a 4-Gb DDR6 part ready to go right behind it.” He estimated that development would take about three years.

At the edge, he argued, MRAM can cut how often data has to travel between devices and central servers for processing, citing OpenMV as an application in which Everspin has replaced SRAM and added MRAM for configuration.

An AI Server Partnership That Is Still an Evaluation

Everspin signed a memorandum of understanding (MoU) with MaxLinear to evaluate MRAM next to MaxLinear's storage compression, encryption and hardware acceleration platform for AI servers. Scope: metadata management, log data, write buffering, cache and other data-intensive workloads. The two also plan technical validation and market development targeting hyperscale cloud providers, AI infrastructure developers and enterprise server customers, with potential longer-term manufacturing, supply and commercialization possibilities.

MaxLinear came first for a specific reason. “They have accelerators, so they were very interested in the technology,” Aggarwal said. “We are working with them to find the first use case.”

Worth repeating for readers who skim press releases: the MoU establishes an evaluation framework. It does not announce a finished product or a volume commitment.

From Test Bench to Orbit

Earlier this year, Astro Digital selected Everspin's 64Mb PERSYST spin-transfer torque MRAM (STT-MRAM), part number EM064LXQADG13IS1T, as the primary fail-safe memory for the boot process on its Raven satellite bus, for a geosynchronous Earth orbit (GEO) mission. Boot memory holds the code that starts a spacecraft's electronics and supports system recovery.

“What Astro Digital did recently was, they took our part and sent it into geosynchronous orbit,” Aggarwal said. “So, not low Earth, but they sent those to geosynchronous orbit.”

Radiation tolerance is the appeal in space, he said, with the caveat that the surrounding silicon can still be vulnerable to radiation damage; in the configuration he described, a backup memory adds a safeguard if nearby circuitry is affected. He also pointed to write speed and reliability versus NOR flash, saying the memory can be written almost three orders of magnitude faster than NOR flash and draws less power in the applications he described. The PERSYST family lists 64-Mb, 128-Mb, and 256-Mb capacities and uses a quad serial peripheral interface (QSPI).

One caution from the interview itself: Aggarwal also gave a general example of how MRAM could reduce chip count in some applications, but the comparison should not be read as a description of Astro Digital's actual satellite configuration.

Who Actually Makes the Chips

Everspin ships two main families: field-switched, or toggle, MRAM and STT-MRAM. Toggle MRAM is produced at its 8-inch facility in Chandler, Arizona, and the portfolio runs from 128 kilobits to 1 Gb across several densities and interfaces. Aggarwal said the company had shipped more than 200 million units over 20 years, with only a handful of returns.

Earlier this year the company signed an initial 10-year foundry services agreement with Microchip Technology to stand up an 8-inch MRAM and tunnelling magnetoresistance (TMR) sensor line at Microchip's Fab 4 facility in Gresham, Oregon, creating a second U.S. manufacturing source for toggle MRAM. The U.S. SEC filing stated that first products are expected to ship in the second half of 2027.

“We signed a foundry services agreement with Microchip, which allows me to manufacture twice the amount of toggle MRAM that I could manufacture in Chandler,” Aggarwal said.

That deal is connected to a $40 million U.S. government contract awarded through Amentum Services, with Everspin acting as a subcontractor. The work, he said, will qualify its process at Microchip and give the government access to the company's intellectual property and a second line for future government products.

On the STT side, Everspin has worked with GlobalFoundries on 12-inch wafers since 2016, and plans to tape out a product using TSMC's 16-nm process, which Aggarwal said would diversify supply. The target is two manufacturing sources for both families: Chandler and Oregon for toggle MRAM, GlobalFoundries and TSMC for STT-MRAM. Capacity, he said, is not currently a constraint.

Competition exists in commercial MRAM: South Korean company Netsol, which uses Samsung Foundry, offers a 16-Mb product, and Aggarwal expects a 1-Gb product from that competitor to reach the market in 2028 or 2029.

India: The Next Set of Doors

India is another candidate market, especially in aerospace and defense, electric vehicles and railways. Aggarwal said he was seeking connections with the Defence Research and Development Organisation (DRDO), the Indian Space Research Organisation (ISRO) and Indian satellite companies. He identified battery management systems and vehicle data recorders as possible applications, alongside flight control systems, and said Everspin is working to widen its Indian distribution network, exploring local partnerships that include discussions with Indian distributors and possible outsourced semiconductor assembly and test (OSAT) arrangements.

On rail, he cited existing deployments in Europe, Japan and China, where memory stores operational data. “We are always in discussions about these potential opportunities,” he said of Indian railway opportunities. “There is nothing that I can talk about openly, but obviously the conversations are ongoing.”

Four Misconceptions to Avoid

• “This is purely a price story.” Customers are weighing performance and reliability alongside availability; the narrower cost gap is an accelerant, not the whole argument.
• “Any non-volatile memory can slot in.” The interview flags FRAM's lower available densities and NVSRAM's tradeoffs in reliability and operating conditions.
• “The satellite design uses MRAM everywhere.” The chip-count example was general, not a description of Astro Digital's actual configuration, and surrounding silicon can still be radiation-vulnerable.
• “The AI-server deal is a product launch.” The MaxLinear MoU is an evaluation framework, with no announced finished product or volume commitment.

FAQ

Is MRAM already replacing NOR flash in shipping products?

Nothing in this account says so. The substitute is described as a product Everspin has been developing on TSMC's process, sized by Aggarwal as a $3 billion opportunity in 2028 or 2029.

Why would a designer pay more per chip?

Because board-level math can flip: once MRAM sits at about 1.5 times the price instead of about three times, one MRAM part can beat two NOR flash parts on cost-effectiveness, in Aggarwal's framing.

Is capacity enough for AI jobs?

Today a single device tops out at one gigabit, stackable in principle to 8 Gb or 16 Gb, and capacity remains a limitation. The proposal is a temporary holding tier for KV caches and checkpoints, not a NAND replacement.

What would show this pivot is working?

Dates and dollars: first Microchip-line products expected in the second half of 2027, a 4-Gb DDR6 part roughly three years out behind the current DDR4 chip, and a plan to double revenue over three to four years.

Action Checklist: What to Do With This

1. Ask distributors for cross-reference options now, before a build is scheduled around one hard-to-get NOR flash part.
2. Re-run the chip-count math: compare two NOR flash devices against one MRAM device on price, board space and endurance.
3. Match specifications, not slogans: confirm whether you need the minus 40°C to 125°C operating range and the reliability profile.
4. Treat MoUs as trials: separate evaluation frameworks from volume commitments when you read infrastructure announcements.
5. Track second-source timing, especially the Chandler plus Oregon and GlobalFoundries plus TSMC pairings.
6. If you follow AI infrastructure, watch whether a persistent tier between DRAM and NAND gets designed in, using the CXL demo as the reference point.

The through-line for MyTechDailyNews readers is simple: a shortage has handed a long-overshadowed memory type an audition in three very different venues at once — the AI rack, the satellite bus and the factory floor. Whether the audition turns into regular work depends on densities, cost per bit as manufacturing efficiencies improve, and second sources that are still being qualified. Aggarwal's own expectation is that demand grows as those conditions fall into place; the market's verdict will show up in the product dates listed above.